This invention relates generally to an electronic timepiece, and more particularly to an electronic timepiece which is adjusted for inaccuracies of the oscillator circuit by periodic setting of the logic state of stages in the divider network in accordance with externally applied data. In a timepiece using a plurality of divider stages to divide down the high frequency signal of an oscillator, perfect timekeeping results when the oscillator outputs its signal at a precise frequency. However, because of an inability to precisely control all parameters in the manufacture of the oscillator circuit, an exact frequency signal is rarely produced. Corrections for these inaccuracies can be made within the oscillator circuit itself but this is costly and provides a limited range of adjustability.
What is needed is a timepiece where corrections for inaccuracies in the frequency signal output of the oscillator circuit are made in the divider stages to which the uncorrected signals are inputted.